Helios
This product is supported for DSCUD 8.0 and above.
Overview
Helios's Data Acquisition circuitry is similar to that on Athena-II but some of the registers for controlling the behavior of the circuit are different on Helios from Athena II.
The Universal Driver handles the differences. Below are some of the major differences in the Helios board.
1. Watchdog Timer support.
2. Additional DIO ports available in Helios.
3. DA modes are software programmable.
4. DA channels can be individually programmed for unique range settings.
In case of Helios board, all the AD and DA settings are only software programmable. Unlike the previous boards, jumpers cannot be used to perform the AD / DA mode and polarity settings.
Board Initialization
To use the Helios board in an application using the UD, the dscInitBoard function should use the board macro DSC_HELIOS. This is shown in the example below... The base address should be 0x280 ( or whatever is set in the BIOS of the board) and the default IRQ to use is IRQ 5.
It is highly recommended that the dsccb structure be memset to 0 in the application before calling the dscInitBoard API.
The Helios board also uses the DAC_Config element available in the DSCCB structure to force 16 bit DAC operation. To use the 16 bit DAC mode of the Helios board, the DAC_Config element of the DSCCB structure must be set to 1 before calling the dscInitBoard API.
dsccb.DAC_Config = 1 ; // for 16 bit mode DAC.
Currently Helios boards have only 12 bit DAC available and thus it is advisable to set the DAC_Config to 0.
NOTE: For making the interrupt based operations work on Helios board, the IRQ5 MUST be set to Reserved in the BIOS.
Analog Input
FIFO:
48 samples with programmable threshold in standard mode.
Upto 2048 in Enhanced FIFO mode.
In the enhanced FIFO mode, it is recommended to set the FIFO threshold to 1024 samples by setting the FIFO threshold register Base + 5 with a value of 0x80. The FIFO threshold register at location Base + 5 of the Helios board, contains the threshold for the enhanced mode. The threshold is an 11 bit number as the maximum FIFO depth available in Helios is 2048. Thus to set the threshold value of 11 bit in an 8 bit register, the threshold value is programmed as 8 sample blocks. The universal driver takes care of the conversion.
For example, to set a FIFO threshold of 1024, the Universal Driver will write a value of 0x80 to the register.
Analog Output
The Helios board provides the following programmable DA modes. The DA modes can be set using a new API function called dscDASetSettings ().
Digital I/O
Helios supports 5 DIO ports. All the DIO ports are bi-directional, programmable in 8-bit groups, TTL-compatible and are similar to 82C55 Digital I/O ports on AthenaII. All the ports require the port direction to be set with dscDIOSetConfig before use. The value of 0x00 is used for the port to be an output port while 0xFF configures the port as an input port.
The Helios board supports 3 DIO ports which are 82C55 based ports provided by the on-board FPGA. There are 2 more DIO ports made available to the user which are directly provided by the CPU.
All DIO lines power-up in input mode and have readback capability.
Helios Universal Driver Functions
Last updated