14.1 Overview

The data acquisition circuit on the AV model of Helios uses an FPGA which is attached to the ISA bus. It is accessible via a 16-byte window in ISA I/O space. It can be enabled or disabled in the BIOS. Select Chipset, then South Bridge Configuration, then GPCS. Select “Enabled” or “Disabled”, and then select the desired base address. The default settings are Enabled and address = 280 (meaning 0x280 – 0x28F). The

available address options are: 200, 240, 280, 2C0, 300, 340, 380, 3C0

If the FPGA is disabled you will not be able to use the data acquisition circuit. The chosen address must not conflict or overlap with any other CPU feature or installed add-on board. Most Diamond I/O boards have a default I/O address of 300, so that address should not be used for the on-board data acquisition if a Diamond I/O board is installed.

The table below provides a high level overview of the register functions. Detailed bit by bit descriptions are in the next section.

Base +	Write Function	Read Function
0	Main Registers
1	Command	A/D LSB (bits 7-0)
2	Page Register	A/D MSB (bits 15-8)
3	A/D Channel Range	A/D Channel Range Read-back
4	A/D Gain and Scan Settings	A/D Gain Read-back, A/D & D/A status
5	Interrupt / Counter Control	Interrupt / Counter Control Read-back
6	FIFO Threshold	FIFO Threshold Read-back
7	D/A LSB	FIFO Current Depth / FIFO Status
8	D/A MSB / D/A Channel	Interrupt and A/D Channel Read-back
9	Digital I/O Port A Output	Digital I/O Port A Input
10	Digital I/O Port B Output	Digital I/O Port B Input
11	Digital I/O Port C Output	Digital I/O Port C Input
12	Digital I/O / DA Control	Digital I/O / DA Control Read-back
	Page 0: Counter/Timers
12	Counter/Timer 0/1 D7-0	Counter/Timer 0/1 D7-0
	Counter/Timer 0/1 D15-8	Counter/Timer 0/1 D15-8
	Counter/Timer 0 D23-16	Counter/Timer 0 D23-16
	Counter/Timer Control	FPGA Revision Code
	Page 1: Autocalibration Control
	EEPROM/TrimDAC data latch	EEPROM/TrimDAC data read-back
	EEPROM/TrimDAC address latch	EEPROM/TrimDAC address read-back
	EEPROM/TrimDAC control register	EEPROM/TrimDAC status register
	EEPROM Access Code
	Page 2: Expanded FIFO, A/D & D/A Configuration
	Expanded FIFO depth register	Expanded FIFO depth read-back
	AD Mode Configuration	AD Mode Configuration Read-back
	DA Mode Configuration	DA Mode Configuration Read-back
	DA MSB (16-bit Mode)	DA Simultaneous Update