3. Watchdog Timer Configuration Steps
3.1 Configure Watchdog Timer
The register map consists of several 16-byte pages that are accessed via a 16-byte window. The page is selected with register 15 in each page. Watchdog configuration registers are present in page 8. Please refer Aries user manual page number 32, jumper block JP4 settings for base address.
Steps:
Write 0x8 to baseaddress+0xF to select page 0x8
Write counter A LSB value to baseaddress+0x8
Write Counter A MSB value to baseaddress+0x9
Write Counter B value to baseaddress+0xA
Write watchdog timer configuration register at baseaddress+0xB, the register bits are as follows:
WDINTEN bit: [1 = Enable interrupt, 0 = Disable interrupt]
WDT-1 bit: [WDT-1= 1: DIO C4 goes high when counter A = 1 instead of 0, i.e. 1 count early. This enables C4 to be externally wired to C5 to cause an automatic repetitive retrigger when WDIEN = 1 and WDEDGE = 0. WDT-1= 0: C4 will not go high when counter A = 1]
WDIEN bit: [1 = Enable hardware retrigger of counter. 0 = Disable hardware retrigger of counter]
WDEDGE bit: [1 = Interrupt on falling edge. 0 = Interrupt on rising edge]
Register interrupt handler, if you are enabling interrupt.
3.2 Enable Watchdog Timer
Watchdog timer enable bit is present in the configuration register in page 0x8 at offset 0xB.
Steps:
Write 0x8 to baseaddress+0xF to select page 0x08.
Set WDTEN bit in register at baseaddress + 0xB without affecting other bits to enable watchdog timer.
3.3 Disable Watchdog Timer
Watchdog timer is disabled by writing 0 to configuration register. Configuration register is present at address baseaddress+0xB in page 0x8
Steps:
Write 0x8 to baseaddress+0xF to select page 0x8
Write 0 to register at baseaddress+0xB to disable watchdog timer.
Unregister interrupt handlers for Watchdog timer, if you have registered any.
3.4 Software Re-trigger For Watchdog Timer
Software retrigger is done by setting WDTRIG bit in watchdog timer configuration register. It will reload the Counter A and counter B with initial value which was loaded at the watchdog timer configuration time. If this function is called prior to Counter A reaches 0, it avoids the hardware reset.
Steps:
Write 0x8 to baseaddress+0xF to select page 0x8
Read watchdog timer configuration value from register at baseaddress+0xB and check whether WDIEN bit is set.
If WDIEN bit is set, it means that hardware retrigger is enabled. So we can’t do software retrigger.
If hardware retrigger is not enabled, write 0x80 to baseaddress+0xB to do software retrigger.
3.5 Test Watchdog Timer Configuration
Steps:
Check and confirm that the base address is proper according to JP4 jumper settings
Configure the Watchdog timer according to configuration steps.
Check software retrigger of watchdog timer by writing 0x80 to baseaddress+0xB and make sure that system reset doesn’t happen or registered interrupt is not called.
Check hardware retrigger of watchdog timer by connecting C4 to C5 and make sure that system reset doesn’t happen or registered interrupt is not called.
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