14.1 Description

Page 5 of the upper I/O map provides control for the D/A waveform generator. The D/A waveform generator uses an in-FPGA memory block of 1024 words to store D/A codes. The FPGA parses through this memory at a user-programmable speed (or through manual/external trigger) while sending codes to the D/A converter. The generator automatically stops if enhanced features are disabled.

The generator works in frames. A new frame is triggered from a programmable source (manual, counters, external, etc.) For each frame, the FPGA sends a programmable (1, 2 or 4) number of D/A codes from the generator’s memory bank straight to the DAC. This transfer is done in latched mode, and the DAC is updated after all codes in a frame are sent. The generator continues this process, incrementing through the memory until it reaches the end of the buffer, or hits a programmable depth – at which point it will wrap back to the beginning of the buffer and continue operation. The generator can be paused, resumed or reset to the beginning of the memory bank at any time.

With the use of the memory block the D/A waveform generator can output consistent waveforms at a maximum frequency of 100KHz. There are four different input sources available for the D/A waveform generator: manual software trigger, counter 0 output, counters 1+2 output, and external trigger. The memory block also allows a programmable depth which when hit, will wrap and return to the beginning. The threshold ranges from 64 to 1024 and is programmable in multiples of 64.