Table of Contents

General Description

Overview

Digital I/O Features

Counter/Timer Features

Enhanced Features

Board Layout

Board Drawing

I/O Connector Pinout

Digital I/O Header Pinout

Counter/timer Header Pinout

Auxiliary I/O Header Pinout

Board Configuration

Base Address Selection

Interrupt Level Selection

I/O Line Pull-up/Pull-down Selection

I/O Map

Overview

Counter/Timer and Enhanced Feature Programming

DIO Programming

Register Summary

Register Bit Descriptions

9513 Control/Status Data

9513 Control/Status Pointer

9513 DIO Input Data

9513 DIO Output Data

9513 Interrupt Enable/Disable

9513 Interrupt Reset

EEPROM Data

EEPROM Address

EEPROM Status

EEPROM Control

FPGA Revision Code

Select Clock Source

Interrupt Source

Interrupt Status

Interrupt Control

Auxiliary DIO Control

Board Reset

Board ID

8255 Data

8255 Control and Status (Basic Mode Definition–MSFLAG=1)

8255 Control and Status (Bit SET/RESET Mode – MSFLAG=0)

Programming the Counter/Timer

Overview

Accessing the Counter/Timer Internal Registers

Master Mode Register

Counter Mode Register

Counter Modes

FOUT Frequency Output

Counter Commands

Counter Programming

Programming Digital I/O

48-bit Programmable Direction (8255)

16-bit Fixed Direction (9513)

Programming Enhanced Features

EEPROM Programming

Specifications

General Specifications

Additional Information

Datasheets

Technical Support

Figures

Figure 1: GPIO-MM Board Layout

Figure 2: Example - Set DIO Base Address to 0040h

Figure 3: Example - Set Counter/Timer Base Address to 0100h

Figure 4: Example - Route IRQA to PC/104 IRQ5

Figure 5: Example - Connect IRQA to Pull-down Resistor and Route to Shared IRQ5

Figure 6: Example - Pull I/O Pins Up to +5VDC

Figure 7: Example - Pull I/O Pins Down to Ground