Digital I/O Operation

This page describes the operation of Digital I/Os of the DAQ subsystem available on Athena IV.

Athena IV contains 24 digital I/O lines organized as three 8-bit I/O ports: Port A, Port B, and Port C. The direction of each port is programmable, and port C is further divided into two 4-bit halves, each with independent direction. The port data are accessed at registers Base+8 through Base+10, and the port direction register is located at Base+11.

Base +	7	6	5	4	3	2	1	0
8	PA7	PA6	PA5	PA4	PA3	PA2	PA1	PA0
9	PB7	PB6	PB5	PB4	PB3	PB2	PB1	PB0
10	PC7	PC6	PC5	PC4	PC3	PC2	PC1	PC0
11	DIOCTR	-	-	DIRA	DIRCH	-	DIRB	DIRCL

The digital I/O lines are located at pins 1 through 24 on the I/O header J14. The lines are 3.3V output compliant and 5V logic input tolerant. Each output is capable of supplying –12mA in logic 1 state and +24mA in logic 0 state.

DIRA, DIRB, DIRCH, and DIRCL control the direction of ports A, B, C4-7 and C0-3. A direction value of 0 means output and 1 means input. All ports power up to input mode and the output registers are cleared to zero. When a port direction is changed to output, its output register is cleared to zero. When a port is in output mode, its value can be read back.

DIOCTR is used to control the function of lines C7-C4 on the I/O connector. When DIOCTR = 1, the lines are port C7-C4. When DIOCTR = 0, the lines are used for the counter/timer.

Pin No.	DIOCTR = 1	DIOCTR = 0	Pin direction for DIOCTR = 0
21	C4	Gate0	Input
22	C5	Gate1	Input
23	C6	Clk1	Input
24	C7	Out0	Output