21.3 Digital Interrupts

The data acquisition circuit on the AV model can generate interrupts on the ISA bus when a rising edge occurs on the EXTTRIG pin (J17 pin 25). This pin is pulled high when unconnected. The interrupt occurs on the IRQ level configured with jumper block J21. To enable digital interrupts, set bit DINTE=1 (base+4 bit 1). To generate an interrupt, drive pin 25 low and then high again (or release it to open circuit). To detect if an interrupt has occurred, read the DINT status bit (base+7 bit 5). A 1 = interrupt pending, 0 = no interrupt pending. To clear the interrupt request, write a 1 to the CLRD bit (base+0 bit 1) or disable digital interrupts by setting DINTE=0.

When an interrupt is pending, the IRQ line will be driven high. When no interrupt is pending, the board will release the IRQ line and it will be pulled low by the pull-down resistor configured with J21. It is possible for Helios to generate interrupts from up to 3 sources simultaneously. Thus clearing one interrupt will not necessarily cause the IRQ line to go low. It will only go low when all 3 circuits are inactive or have no interrupts pending.