19.5 Update the D/A

The DASIM bit (base+11 bit 5) determines when the D/A will be updated. If the D/A is not set up for simultaneous operation (DASIM=0), then writing the channel number to base+7 will automatically update the selected D/A channel with the new data. The update takes approximately 4uS to complete. No writes should occur to the DAC while an update is in progress. While the update is occurring, the DACBSY bit in base+3 bit 4 will be 1. You can monitor this bit to wait for the update to finish if there is a possibility that your application will attempt to access the DAC before the update completes. To prevent software from hanging due to a hardware error, a timeout should be built into the checking.

// this will exit if DACBSY = 0 or loop reaches terminal count

for (i=0; i<100000; i++) if (inp(base+3) & 0x10 == 0) break;

If DASIM=1, the DAC is set up for simultaneous mode, meaning that an update will only occur when a specific update command is issued to the DAC. This lets you preload multiple channels with new data and then update them all at the same time. First load data into the DACs in the standard manner as described above, then issue the update command by reading from page 2 base+15. The value read has no meaning and should be ignored. Note that the simultaneous update command always updates all 4 channels. Any channel with new data will change to reflect the new data. Any channel which has not been changed since it was last updated will simply reload the same value and therefore will remain steady.

outp(base+1, 2); // select page 2

a = inp(base+15); // read register to update all DACs