1. Watchdog Timer Operation

The watchdog timer consists of two down counters and an output logic circuit. Counter A is 16 bits and is loaded with WDA15-0. Counter B is 8 bits and is loaded with WDB7-0. When the WDT is running, each counter is clocked by an internal 100Hz clock, providing for a maximum timeout periods of 655 seconds for timer A and 2.56 seconds for timer B. Digital I/O lines C5 and C4 are assigned as watchdog timer I/O signals when the watchdog timer is in use.

WDTEN = 1 enables the watchdog counter to run and forces DIO C5 to input and DIO C4 to output. DIO C4 is initially set to 0. Setting WDTEN = 1 also causes counters A and B to be loaded with the values in WDA15-0 and WDB7-0. Setting WDTEN = 0 stops the counters, disables the watchdog timer circuit, and returns DIO C4 and C5 to their previous configuration and values.

When running, the watchdog timer may be retriggered in two ways:

• Writing a 1 to the WDTRIG command bit (software retrigger). If WDTRIG = 1 the remaining bits in the WDT control register are not affected.

• If WDIEN = 1, then an edge on DIO pin C5 (hardware retrigger). WDEDGE = 0 selects rising edge, and WDEDGE = 1 selects falling edge.

A retrigger causes the following events to occur:

• Both counters A and B are reloaded with their respective values.

• DIO pin C4 is cleared to 0.

When the watchdog timer circuit is running, initially counter B is idle, and counter A counts down. When Counter A reaches 0, several events occur:

• Output pin DIO C4 goes high to provide an indicator to an external circuit of the counter timeout.

• Counter B starts to count down.

• If WDINTEN = 1, then WDINT = 1 and an interrupt will occur.

If WDINTEN = 1 and WDBINTE = 0, then when counter A reaches 0 an interrupt will occur. The interrupt routine must respond within the time indicated by counter B’s value by either issuing a WDTRIG command or disabling the watchdog timer by setting WDTEN = 0, otherwise the action selected with WDBINTE will occur once counter B reaches 0.

Issuing a WDICLR command or disabling the watchdog timer with WDTEN = 0 clears the WDINT bit. This is separate from the retrigger. If WDICLR = 1 the remaining bits in the WDT control register are not affected.

If WDT-1 = 1, then DIO C4 goes high when counter A = 1 instead of 0, i.e. 1 count early. This enables C4 to be externally wired to C5 to cause an automatic repetitive retrigger when WDIEN = 1 and WDEDGE = 0.