Counter/Timer Features

• Dual CTS9513 counter/timers logic implemented in FPGA cores.

• A 40MHz clock input, providing higher precision timer functions.

• Timing functions are software programmable, using control registers.

• Ten 16-bit programmable up/down counters with sophisticated timing logic:

  • Up or down counting.

  • Binary or BCD counting.

  • Single or repetitive counting.

  • Edge or level gating

  • Output pulse or toggle capability.

  • Alarm comparator circuitry.

  • Software or hardware retriggering.

• 8-bit TTL input and 8-bit TTL output ports, which can operate in bit- or byte mode.

• An interrupt line for generating interrupts to the CPU.

• An external 50-pin header for connecting to the counter/timer features.