6.1 I/O Map Description

Base +	Write Function	Read Function
	Main Registers
0	Start A/D Conversion	A/D LSB (bits 7-0)
1	Auxiliary digital output	A/D MSB (bits 15-8)
2	A/D low channel register	A/D low channel read-back
3	A/D high channel register	A/D high channel read-back
4	D/A LSB register	Auxiliary digital input
5	D/A MSB + channel register
6	FIFO threshold register	FIFO depth register
7	FIFO control register	FIFO status register
8	Miscellaneous and page control register	Status register
9	Operation control register	Operation status register
10	Counter/timer control register	Counter/timer control read-back
11	Analog configuration register	Analog configuration read-back
	Page 0: 82C54 Counter/Timer Access
12	Counter 0 data	Counter 0 data read-back
13	Counter 1 data	Counter 1 data read-back
14	Counter 2 data	Counter 2 data read-back
15	82C54 control register	82C54 control register read-back
	Page 1: 82C55-Type Digital I/O
12	Port A Output	Port A Input
13	Port B Output	Port B Input
14	Port C Output	Port C Input
15	DIO control register	DIO control register read-back
	Page 2: FIFO Control (Enhanced Feature Page)
12	Expanded FIFO depth register	Expanded FIFO depth read-back
13
14
15
	Page 3: Autocalibration Registers
12	EEPROM/TrimDAC data latch	EEPROM/TrimDAC data read-back
13	EEPROM/TrimDAC address latch	EEPROM/TrimDAC address read-back
14	EEPROM/TrimDAC control register	EEPROM/TrimDAC status register
15	Special features unlock register0	FPGA revision code
	Page 4: dsPIC Interface (Enhanced Feature Page)
12	dsPIC data latch	dsPIC data latch
13	dsPIC address latch	dsPIC address latch
14	dsPIC control register	dsPIC status register
15	dsPIC programming control	dsPIC programming status
	Page 5: D/A Waveform Generator (Enhanced Feature Page)
12	Waveform address latch (LSB)	Waveform address latch (LSB)
13	Waveform address latch (MSB)	Waveform address latch (MSB)
14	Waveform configuration register	Waveform configuration read-back
15	Waveform command register
	Page 6: CPLD I/O Window (Enhanced Feature Page)
12
13
14	This page is a window to the CPLD I/O. This page should not be accessed under normal operation.
15
	Page 7: D/A Channel Control (Enhanced Feature Page, When Enabled by DAC_CONT)
12	D/A Channel A Control	D/A Channel A Control
13	D/A Channel B Control	D/A Channel B Control
14	D/A Channel C Control	D/A Channel C Control
15	D/A Channel D Control	D/A Channel D Control