17.2 Counter/Timer Configuration

The counter/timer configuration is determined by the control register at Base + 10 described on page 23. Note that the outputs of counters 0 and 2 are routed to pins on I/O header J3 under software control rather than being hardwired. Configuring the A/D sampling clock is done with the control register at Base + 9 described on page 22. Bit CLKEN selects whether the A/D hardware clocking is enabled, and if so, bit CLKSEL selects whether it is the output of counter/timer 2 or the external clock input at Extclk / Din3 on J3.