DAQ Register Map

This page describes the register map provided on the DAQ subsystem available on Athena IV.

13.1 Data Acquisition Circuitry I/O Map

13.1.1 Overview

The data acquisition circuitry on Athena IV occupies 16 bytes in I/O memory space. The default address range is 280h (base address) to 28Fh.

13.1.2 Register Map Page Summary

The following table summarizes the DAC register functions. The registers are paged to allow access to enhanced functions. There are three register pages and the desired page is selected using the A/D gain and scan settings register, Base+3, bits PG0-PG1, provided the board is in enhanced mode.

Base +	Write Function	Read Function
DAQ Main Registers
0	Command	A/D LSB (bits 7-0)
1	Enhanced Mode Control/Page setting	A/D MSB (bits 15-8)
2	A/D Scan Channel	A/D Scan Channel L/H Read-back
3	A/D Gain and Scan Settings / Page Control	A/D-D/A Gain and Status Read-back
4	Interrupt / Counter Control	Interrupt / Counter Control Read-back
5	FIFO Threshold	FIFO Threshold Read-back
6	D/A LSB	FIFO Current Depth / FIFO Status
7	D/A MSB / DAC Channel	Interrupt and A/D Channel Read-back
8	Digital I/O Port A Output	Digital I/O Port A Input
9	Digital I/O Port B Output	Digital I/O Port B Input
10	DigitalI/OPort C Output	Digital I/O Port C Input
11	Digital I/O / DA Control	Digital I/O / DA Control Read-back
DAQ Registers Page 0: Counter/Timer Access
12	Counter/Timer D7-0	Counter/Timer D7-0
13	Counter/Timer D15-8	Counter/Timer D15-8
14	Counter/Timer D23-16	Counter/Timer D23-16
15	Counter/Timer Control	FPGA Revision Code
DAQ Registers Page 1: AutoCal Control
12	EEPROM/TrimDAC data latch	EEPROM/TrimDAC data read-back
13	EEPROM/TrimDAC address latch	EEPROM/TrimDAC address read-back
14	EEPROM/TrimDAC control register	EEPROM/TrimDAC status register
15	Special features unlock register0	Page 1 ID Read-back
DAQ Registers Page 2: Expanded FIFO and AD /DA Control
12	Expanded FIFO depth register	Expanded FIFO depth read-back
13	AD Mode Control	AD Mode Control Read-back
14	A/D scan interval	A/D scan interval
15	DAQ LED, Serial Port Control Register	Page 2 ID Read back
DAQ Registers Page 3: FPGA / Board ID
12	RESERVED	RESERVED
13	RESERVED	RESERVED
14	None, Read only	FPGA Minor ID Read-back
15	None, Read only	FPGA Major ID Read-back
CPLD Watchdog Registers
0	WDT trigger register	None, write only
1	WDT, counter register	None, write only
2	Watchdog Control register	Readback, see details
3	Chip select enable/disable	Readbacks the same written bits

N0TE: 1. Page 0, registers 0-11 are accessible when Page 1 or Page 2 are selected.

2. In the following tables, blank bits are not used. Writes to a blank bit have no effect and reads from a blank bit return a value of zero.

13.1.3 Register Map Bit Summary

Write Register Summary

Base +	7	6	5	4	3	2	1	0
Main Registers
0	STARTAD	RSTBRD	RSTDA	RSTFIFO	CLRDMA	CLRT	CLRD	CLRA
1							PG1	PG0
2	H3	H2	H1	H0	L3	L2	L1	L0
3	-	-	PG1	PG0	-	SCANEN	ADG1	ADG0
4	CKSEL1	FRQSEL1	FRQSEL0	ADCLK	DMAEN	TINTE	DINTE	AINTE
5	- / FT10	- / FT09	FT5/ FT08	FT4/ FT07	FT3/ FT06	FT2/ FT05	FT1/ FT04	FT0/ FT03
6	DA7	DA6	DA5	DA4	DA3	DA2	DA1	DA0
7	DACH1	DACH0	-	-	DA11	DA10	DA9	DA8
8	A7	A6	A5	A4	A3	A2	A1	A0
9	B7	B6	B5	B4	B3	B2	B1	B0
10	C7	C6	C5	C4	C3	C2	C1	C0
11	DIOCTR		DASIM	DIRA	DIRCH	-	DIRB	DIRCL
Page 0: Counter/Timer Access
Base +	7	6	5	4	3	2	1	0
12	CtrD7	CtrD6	CtrD5	CtrD4	CtrD3	CtrD2	CtrD1	CtrD0
13	CtrD15	CtrD14	CtrD13	CtrD12	CtrD11	CtrD10	CtrD9	CtrD8
14	CtrD23	CtrD22	CtrD21	CtrD20	CtrD19	CtrD18	CtrD17	CtrD16
15	CTRNO	LATCH	GTDIS	GTEN	CTDIS	CTEN	LOAD	CLR
Page 1: AutoCal Control
Base +	7	6	5	4	3	2	1	0
12	D7	D6	D5	D4	D3	D2	D1	D0
13	A7	A6	A5	A4	A3	A2	A1	A0
14	EE_EN	EE_RW	RUNCAL	CALMUX	TDACEN	-	-	-
15	-- EEPROM Access Key Register --
Page 2: Expanded FIFO and AD/DA Control
12	-	-	-	-	-	-	-	EXFIFO
13	-	-	DACPOLEN	DACPOL	ADPOL	ADPOLEN	ADSD	ADSDEN
14	-	-	-	-	-	-	-	SCANINT
15	DAQ_LED	-	-	SERCFG	SC3	SC2	SC1	SC0
Page 3: Board IDs
12	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-
14	-	-	-	-	-	-	-	-
15	-	-	-	-	-	-	-	-

Read Register Summary

Base +	7	6	5	4	3	2	1	0
Main Registers
0	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0
1	AD15	AD14	AD13	AD12	AD11	AD10	AD9	AD8
2	H3	H2	H1	H0	L3	L2	L1	L0
3	ADBUSY	SE/DIFF	ADWAIT	DACBSY	OVF	SCANEN	ADG1	ADG0
4	CKSEL1	FRQSEL1	FRQSEL0	ADCLK	DMAEN	TINTE	DINTE	AINTE
5	- / FD07	-/ FD06	FT5/FD05	FT4/FD04	FT3/FD03	FT2/FD02	FT1/FD01	FT0/FD00
6	FD7/FD11	FD6/FD10	FD5/FD09	FD4/FD08	FD3/OVF	FD2/FF	FD1/HF	FD0/EF
7	DMAINT	TINT	DINT	AINT	ADCH3	ADCH2	ADCH1	ADCH0
8	A7	A6	A5	A4	A3	A2	A1	A0
9	B7	B6	B5	B4	B3	B2	B1	B0
10	C7	C6	C5	C4	C3	C2	C1	C0
11	DIOCTR		DASIM	DIRA	DIRCH	-	DIRB	DIRCL
Page 0: Counter/Timer Access
12	CtrD7	CtrD6	CtrD5	CtrD4	CtrD3	CtrD2	CtrD1	CtrD0
13	CtrD15	CtrD14	CtrD13	CtrD12	CtrD11	CtrD10	CtrD9	CtrD8
14	CtrD23	CtrD22	CtrD21	CtrD20	CtrD19	CtrD18	CtrD17	CtrD16
15	-- FPGA Revision Code --
Page 1: AutoCal Control
12	D7	D6	D5	D4	D3	D2	D1	D0
13	A7	A6	A5	A4	A3	A2	A1	A0
14	-	TDBUSY	EEBUSY	CALMUX	-	-	-	-
15	-- 0xA1 --
Page 2: Expanded FIFO and AD/DA Control
12	-	-	-	-	-	-	-	EXFIFO
13	-	-	DACPOLEN	DACPOL	ADPOL	ADPOLEN	ADSD	ADSDEN
14								SCANINT
15	-- 0xA2 --
Page 3: Board IDs
12	-	-	-	-	-	-	-	-
13	-	-	-	-	-	-	-	-
14	Board ID Minor: fixed at 0x08
15	Board ID Major: fixed at 0x16

13.1.4 Main Registers

Base + 0 Write Command Register

Bit No.	7	6	5	4	3	2	1	0
Name	STRTAD	RSTBRD	RSTDA	RSTFIFO	CLRDMA	CLRT	CLRD	CLRA
Reset	X	X	X	X	X	X	X	X

This register is used to perform various functions. The register bits are not data bits but instead command triggers. Each function is initiated by writing a 1 to a particular bit. Writing a 1 to any bit in this register does not affect any other bit in this register. For example, to reset the FIFO, write the value 0x10 (16) to this register to write a 1 to bit 4. No other function of the register will be performed. Multiple actions can be carried out simultaneously by writing a 1 to multiple bits simultaneously.

STRTAD Start an A/D conversion (trigger the A/D) when in software-trigger mode (AINTE = 0). Once the program writes to this bit, the A/D conversion will start and the STS bit (base + 3 bit 7) will go high. The program should then monitor STS and wait for it to go low (check if value in base + 3 is less than 128 or 0x80). When it goes low the A/D data at Base + 0 and Base + 1 may be read.

When AINTE = 1 (base + 4 bit 0), the A/D cannot be triggered by writing to this bit. Instead the A/D will be triggered by a signal selected by ADCLK in base + 4 bit 5.

RSTBRD Reset the entire board excluding the D/A. Writing a 1 to this bit causes all registers on the board to be reset to 0. The effect on the digital I/O is that all ports are reset to input mode, and the logic state of their pins will be determined by the pull-up/pull-down configuration setting selected by the user. All A/D, counter/timer and interrupt functions will cease. However the D/A values will remain constant.

RSTDA Reset the 4 analog outputs. The analog outputs will be reset to zero volts.

RSTFIFO Reset the FIFO depth to 0. This clears the FIFO so that further A/D conversions will be stored in the FIFO starting at address 0.

CLRDMA Writing a 1 to this bit causes the DMA interrupt request flip flop to be reset.

CLRT Writing a 1 to this bit causes the timer interrupt request flip flop to be reset.

CLRD Writing a 1 to this bit causes the digital I/O interrupt request flip flop to be reset.

CLRA Writing a 1 to this bit causes the analog interrupt request flip flop to be reset.

The user’s interrupt routine must write to the appropriate bit prior to exiting in order to enable future interrupts. Otherwise the interrupt line will stay high indefinitely, and no additional interrupt requests will be generated by the board.

Base + 0 Read A/D LSB

Bit No.	7	6	5	4	3	2	1	0
Name	AD7	AD6	AD5	AD4	AD3	AD2	AD1	AD0
Reset	0	0	0	0	0	0	0	0

AD7 - 0 A/D data bits 7 - 0; AD0 is the LSB; A/D data is an unsigned 16-bit value.

The A/D value is derived by reading two bytes from Base + 0 and Base + 1 and applying the following formula:

A/D value = (Base + 0 value) + (Base + 1 value) * 256

The value is interpreted as a twos complement 16-bit number ranging from –32768 to +32767. This raw A/D value must then be converted to the corresponding input voltage and/or the engineering units represented by that voltage by applying additional application-specific formulas. Both conversions (conversion to volts and then conversion to engineering units) may be combined into a single formula for efficiency.

Base + 1 Write Enhanced Features Access Register

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	PG1	PG0
Reset	0	0	0	0	0	0	0	0

This register has dual function. When 0xA5 and 0xA6 is written to this register nothing happens and the page bits PG1-0 are preserved. The 0xA5, 0xA6 functionality is kept to provide backward compatibility with existing code. In order to change the page, the PG1-0 bits should be changed. These bits are duplication of the page bits in Base + 3 register.

This register is different than in Athena-II and provides faster performance to access registers in other pages.

Page Select (0 - 2): Accessible any time to select any of the 3 pages.

Base + 1 Read A/DMSB

Bit No.	7	6	5	4	3	2	1	0
Name	AD15	AD14	AD13	AD12	AD11	AD10	AD9	AD8
Reset	0	0	0	0	0	0	0	0

AD15 - 8 A/D data bits 15 – 8; AD15 is the MSB; A/D data is an unsigned 16-bit value.

See Base + 0 Read on the previous page for information on A/D values and formulas.

Base + 2 Read/Write A/D Channel Register

Bit No.	7	6	5	4	3	2	1	0
Name	H3	H2	H1	H0	L3	L2	L1	L0
Reset	0	0	0	0	0	0	0	0

H3 – H0 High channel of channel scan range

Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode.

L3 - L0 Low channel of channel scan range

Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode.

The high channel must be greater than or equal to the low channel.

When this register is written, the current A/D channel is set to the low channel, so that the next time an A/D conversion is triggered the low channel will be sampled.

When this register is written to, the WAIT bit (Read Base + 3 bit 5) will go high for 10 microseconds to indicate that the analog input circuit is settling. During this time an A/D conversion should not be performed because the data will be inaccurate. After writing a new gain setting (Base + 3), the ADWAIT bit is also set, and the program must monitor it prior to starting an A/D conversion. The channel and gain registers can be written to in succession without waiting for the intervening ADWAIT signal. Only one ADWAIT period must be observed between the last triggering condition (write to Base + 2 or Base + 3) and the start of an A/D conversion.

The A/D circuit is designed to automatically increment the A/D channel each time a conversion is generated. This enables the user to avoid having to write the A/D channel each time. The A/D channel will rotate through the values betweenLOW and HIGH. For example, ifLOW = 0 and HIGH = 3, the A/D channels will progress through the following sequence: 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ….

Reading from this register returns the value previously written to it.

Base + 3 Write Analog Input Gain / Page Control

Bit No.	7	6	5	4	3	2	1	0
Name	X	X	PG1	PG0	X	SCANEN	ADG1	ADG0
Reset	0	0	0	0	0	0	0	0

PG1-PG0 Page Select (0 - 3): Only accessible when the board is configured on Enhanced Mode. When the board is on standard mode, only page 0 can be accessed.

SCANEN Scan mode enable:

1 Each A/D trigger will cause the board to generate an A/D conversion on each channel in the rangeLOW – HIGH (the range is set with the channel register in Base + 2). TheSTS bit (read Base + 3 bit 7) stays high during the entire scan. The time between A/D samples is determined by the SCANINT bit in page 2. If SCANINT=0, the scan interval is 10us, and if SCANINT=1, the scan interval is 5us.

0 Each A/D trigger will cause the board to generate a single A/D conversion on the current channel. The internal channel pointer will increment to the next channel in the rangeLOW – HIGH or reset toLOW if the current channel is HIGH. TheSTS bit stays high during the A/D conversion.

ADG1-0 Analog input gain. The gain is the ratio of the voltage seen by the A/D converter and the voltage applied to the input pin. The gain setting is the same for all input channels.

When this register is written to, the ADWAIT bit (Read Base + 3 bit 5) will go high for 10 microseconds to indicate that the analog input circuit is settling. During this time an A/D conversion should not be performed because the data will be inaccurate. After writing a new gain setting, the program should monitor the ADWAIT bit prior to starting an A/D conversion.

After writing a new channel selection (Base + 2), the ADWAIT bit is also set, and the program must monitor it prior to starting an A/D conversion.

The channel and gain registers can be written to in succession without waiting for the intervening ADWAIT signal. Only one ADWAIT period must be observed between the last triggering condition (write to Base + 2 or Base + 3) and the start of an A/D conversion.

The following table lists the possible analog input ranges:

ADG1 ADG0 Gain Unipolar Range Bipolar Range

0 0 1 0-10V ±10V

0 1 2 0-5V ±5V

1 0 4 0-2.5V ±2.5V

1 1 8 0-1.25V ±1.25V

Base + 3 Read Analog Input Status

Bit No.	7	6	5	4	3	2	1	0
Name	ADBUSY	SE/DIFF	ADWAIT	DACBSY	OVF	SCANEN	ADG1	ADG0
Reset	0	1	0	0	0	0	0	0

ADBUSY A/D Busy. 1 = A/D conversion or scan in progress, 0 = A/D is idle.

If SCANEN = 0 (single conversion mode), ADBUSY goes high when an A/D conversion is started and stays high until the conversion is finished. If SCANEN = 1 (scan mode enabled), ADBUSY stays high during the entire scan. After starting a conversion in software, the program must monitor ADBUSY and wait for it to become 0 prior to reading A/D values from Base + 0 and Base + 1.

SE/DIFF Single-ended / Differential mode indicator. 1 = Single Ended, 0 = Differential.

ADWAIT A/D input circuit status. 1 = A/D circuit is settling on a new value, 0 = ok to start conversion.

ADWAIT goes high after the channel register (Base + 2) or the gain register (Base + 3) is changed. It stays high for 9 microseconds. The program should monitor this bit after writing to either register and wait for it to become 0 prior to starting an A/D conversion.

DACBSY Indicates the DAC is busy updating (approx. 30 µS). 1 = Busy, 0 = Idle. Do not attempt to write to the DAC (registers 6 and 7) while DACBSY = 1.

OVF FIFO Overflow bit. This bit indicates that the FIFO has overflowed, meaning that the A/D circuit has attempted to write data to it when it is full. This condition occurs when data is written into the FIFO faster than it is read out.

When overflow occurs, the FIFO will not accept any more data until it is reset. The OVF condition is sticky, meaning that it remains true until the FIFO is reset, so the application program will be able to determine if overflow occurs. If overflow occurs, then you must either reduce the sample rate or increase the efficiency of your interrupt routine and/or operating system.

SCANEN Scan mode readback (see Base + 3 Write above).

ADG1-0 A/D gain setting readback (see Base + 3 Write above).

Base + 4 Read/Write Interrupt / Counter Control

Bit No.	7	6	5	4	3	2	1	0
Name	CKSEL1	FRQSEL1	FRQSEL0	ADCLK	DMAEN	TINTE	DINTE	AINTE
Reset	0	0	0	0	0	0	0	0

CKSEL1 Clock source selection for counter/timer 1:

0 = internal oscillator, frequency selected by CLKFRQ1

1 = external clock input CLK1 (DIO C pins must be set for ctr/timer signals)

FRQSEL1 Input frequency selection for counter/timer 1 when CKSEL1 = 1:

0 = 10MHz, 1 = 100KHz

FRQSEL0 Input frequency selection for counter/timer 0.

0 = 10MHz, 1 = 1MHz

ADCLK A/D trigger select when AINTE = 1:

0 = internal clock output from counter/timer 0

1 = external clock input EXTTRIG

DMAEN Enable DMA operation. 1 = enable, 0 = disable.

TINTE Enable timer interrupts. 1 = enable, 0 = disable.

DINTE Enable digital I/O interrupts. 1 = enable, 0 = disable.

AINTE Enable analog input interrupts. 1 = enable, 0 = disable.

NOTE: When AINTE = 1, the A/D cannot be triggered by writing to Base + 0.

Analog output interrupts are not supported on this board.

Multiple interrupt operations may be performed simultaneously. All interrupts will be on the same interrupt level. The user’s interrupt routine must monitor the status bits to know which circuit has requested service. After processing the data but before exiting, the interrupt routine must then clear the appropriate interrupt request bit using the register at Base + 0.

Base + 5 Write FIFO Threshold / FIFO Threshold X8

Bit No.	7	6	5	4	3	2	1	0
Name	X/FT10	X/FT09	FT5/FT08	FT4/FT07	FT3/FT06	FT2/FT05	FT1/FT04	FT0/FT03
Reset	0	0	0	0	0	0	0	0

FT5–0 When EXFIFO = 0 (Basic Mode, See Register Description for Page 2 Base+12)

FIFO threshold. When the number of A/D samples in the FIFO reaches this number, the board will generate an interrupt and set AINT high (Base + 7 bit 4).

The valid range is 1-48. If the value written is greater than 48, then 48 will be used. If the value written is 0, then 1 will be used.

FT10–03 When EXFIFO = 1 (Enhanced Mode, See Register Description for Page 2 Base+12)

FIFO threshold (upper 8 of 11 bits). When the number of A/D samples in the FIFO reaches this number, the board will generate an interrupt and set AINT high (Base + 7 bit 4).

The valid range is 8 – 2048 in steps of 8. When EXFIFO is set to 1 for the first time the FIFO threshold is set automatically to 1024.

The interrupt routine is responsible for reading the correct number of samples out of the FIFO. The interrupt rate is equal to the total sample rate divided by the FIFO threshold. Generally, for higher sampling rates a higher threshold should be used to reduce the interrupt rate. However remember that the higher the FIFO threshold, the smaller the amount of FIFO space remaining to store data while waiting for the interrupt routine to respond. If you get a FIFO overflow condition, you must lower the FIFO threshold and/or lower the A/D sampling rate.

Base + 5 Read FIFO Threshold / FIFO Depth LSB

Bit No.	7	6	5	4	3	2	1	0
Name	X/FD07	X/FD06	FT5/FD05	FT4/FD04	FT3/FD03	FT2/FD02	FT1/FD01	FT0/FD00
Reset	0	0	0	0	0	0	0	0

FT5-0 When EXFIFO = 0 (Basic Mode, See Register Description for Page 2 Base+12)

FIFO threshold. When the number of A/D samples in the FIFO reaches this number, the board will generate an interrupt and set AINT high (Base + 7 bit 4).

FD07-00 When EXFIFO = 1 (Enhanced Mode, See Register Description for Page 2 Base+12)

Current FIFO Depth LSB. This value indicates the lower 8 bits of the number of A/D values currently stored in the FIFO.

Base + 6 Write DAC LSB

Bit No.	7	6	5	4	3	2	1	0
Name	DA7	DA6	DA5	DA4	DA3	DA2	DA1	DA0
Reset	0	0	0	0	0	0	0	0

DA7–0 D/A data bits 7 - 0; This register stores the DA LSB. D/A data is an unsigned 12-bit value. This register must be written to before the MSB, since writing the MSB updates the DAC immediately. (Unless DASIM is enabled)

Base + 6 Read A/D Channel and FIFO Status

Bit No.	7	6	5	4	3	2	1	0
Name	FD7/FD11	FD6/FD10	FD5/FD09	FD4/FD08	FD3/OVF	FD2/FF	FD1/HF	FD0/EF
Reset	0	0	0	0	0	0	0	0

FD7–0 When EXFIFO = 0 (Basic Mode, See Register Description for Page 2 Base+12)

Current FIFO depth. This value indicates the number of A/D values currently stored in the FIFO.

FD11–08 When EXFIFO = 1 (Enhanced Mode, See Register Description for Page 2 Base+12)

Current FIFO depth MSB. This value indicates the upper 4 bits of the number of A/D values currently stored in the FIFO.

OVF FIFO Overflow bit. This bit indicates that the FIFO has overflowed, meaning that the A/D circuit has attempted to write data to it when it is full. This condition occurs when data is written into the FIFO faster than it is read out.

When overflow occurs, the FIFO will not accept any more data until it is reset. The OVF condition is sticky, meaning that it remains true until the FIFO is reset, so the application program will be able to determine if overflow occurs. If overflow occurs, then you must either reduce the sample rate or increase the efficiency of your interrupt routine and/or operating system.

FF FIFO Full Bit. The next conversion will result in an overflow.

HF FIFO Half Full Bit. FIFO is at least half full containing at least 1k words of A/D data.

EF FIFO Empty. FIFO is empty.

Base + 7 Write DAC MSB

Bit No.	7	6	5	4	3	2	1	0
Name	DACH1	DACH0	-	-	DA11	DA10	DA9	DA8
Reset	0	0	0	0	0	0	0	0

DACH1–0 D/A channel. The values written to Base + 6 and Base + 7 update the selected channel immediately unless DASIM is enabled. The update takes approximately 50ns due to the DAC serial interface.

DA11–8 D/A bits 11 - 8; DA11 is the MSB. D/A data is an unsigned 12-bit value. Writing to this register updates the DAC (If DASIM is disabled).

Base + 7 Read Analog Operation Status

Bit No.	7	6	5	4	3	2	1	0
Name	-	TINT	DINT	AINT	ADCH3	ADCH2	ADCH1	ADCH0
Reset	0	0	0	0	0	0	0	0

TINT Timer interrupt status, 1 = interrupt pending, 0 = interrupt not pending.

DINT Digital I/O interrupt status, 1 = interrupt pending, 0 = interrupt not pending.

AINT Analog input interrupt status, 1 = interrupt pending, 0 = interrupt not pending.

ADCH3-0 Current A/D channel. This is the channel that will be sampled on the next conversion.

When any of the bits 6–4 are 1, the corresponding circuit is requesting interrupt service. The interrupt routine must poll these bits to determine which circuit needs service and then act accordingly.

Base + 8 Read / Write Digital I/O Port A

Bit No.	7	6	5	4	3	2	1	0
Name	A7	A6	A5	A4	A3	A2	A1	A0
Reset	0	0	0	0	0	0	0	0

These registers are used for digital I/O on PortA. The direction of each register is controlled by the DIO control register at Base+11.

Base + 9 Read / Write Digital I/O Port B

Bit No.	7	6	5	4	3	2	1	0
Name	B7	B6	B5	B4	B3	B2	B1	B0
Reset	0	0	0	0	0	0	0	0

These registers are used for digital I/O on PortB. The direction of each register is controlled by the DIO control register at Base+11.

Base + 10 Read / Write Digital I/O Port C

Bit No.	7	6	5	4	3	2	1	0
Name	C7	C6	C5	C4	C3	C2	C1	C0
Reset	0	0	0	0	0	0	0	0

These registers are used for digital I/O on PortC. The direction of each register is controlled by the DIO control register at Base+11.

Base + 11 Write Digital I/O and DA Control Register

Bit No.	7	6	5	4	3	2	1	0
Name	DIOCTR		DASIM	DIRA	DIRCH	-	DIRB	DIRCL
Reset	1	X	0	1	1	0	1	1

DIOCTR Selects counter I/O signals or digital I/O lines PL3B(7), PL3A(6), PL2B(5), PL2A(4) on the FPGA pins (Pins 21-24 on J23):

Pin No. DIOCTR = 0 DIOCTR = 1

PL3B(7) PC4Gate 0 DIO

PL3A(6) PC5Gate 1 DIO

PL2B(5) PC6 Clk 1 DIO

PL2A(4) PC7 Out 0 DIO

NOTE: If DIOCTR = 1, then the pin direction is controlled by DIRCH.

This bit resets to 1.

DIRA Port A direction. 0 = output, 1 = input

DIRB Port B direction: 0 = output, 1 = input

DIRCH Port C bits 7-4 direction: 0 = output, 1 = input

DIRCL Port C bits 3-0 direction: 0 = output, 1 = input

DASIM DASIM D/A simultaneous update control. This bit determines when the D/A is updated.

0 = When Base+7 is written, the D/A data is loaded into the D/A and the update command is

sent immediately afterwards.

1 = When Base+7 is written, the 12bit DA values will be loaded into the D/A converter but the update command will not be issued. Instead, a read of the register at Page 2, Base+15 will cause the update of the D/A converter.

Base + 11 Read Digital I/O and DA Control Register Readback

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	DASIM	DIRA	DIRCH	-	DIRB	DIRCL
Reset	0	0	0	0	0	0	0	0

Read-back of Base+11.

13.1.5 Page 0: Counter / Timer Control Registers

Page 0, Base + 12 Read/Write Counter/Timer D7 - 0

Bit No.	7	6	5	4	3	2	1	0
Name	CTRD7	CTRD6	CTRD5	CTRD4	CTRD3	CTRD2	CTRD1	CTRD0
Reset	0	0	0	0	0	0	0	0

This register is used for both Counter 0 and Counter 1. It is the LSB for both counters.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s LSB register will be loaded with this value. When reading from this register, the LSB value of the most recent Latch command will be returned. The value returned is NOT the value written to this register.

Page 0, Base + 13 Read/Write Counter/Timer D15 - 8

Bit No.	7	6	5	4	3	2	1	0
Name	CTRD15	CTRD14	CTRD13	CTRD12	CTRD11	CTRD10	CTRD9	CTRD8
Reset	0	0	0	0	0	0	0	0

This register is used for both Counter 0 and Counter 1. It is the MSB for counter 1 and the middle byte for counter 0.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s associated register will be loaded with this value. For counter 0, it is the middle byte. For counter 1, it is the MSB.

When reading from this register, the associated byte of the most recent Latch command will be returned. The value returned is NOT the value written to this register.

Page 0, Base + 14 Read/Write Counter/Timer D23 - 16

Bit No.	7	6	5	4	3	2	1	0
Name	CTRD23	CTRD22	CTRD21	CTRD20	CTRD19	CTRD18	CTRD17	CTRD16
Reset	0	0	0	0	0	0	0	0

This register is used for Counter 0 only. Counter 0 is 24 bits wide, while Counter 1 is only 16 bits wide.

When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15 for Counter 0, the counter’s MSB register will be loaded with this value. When issuing a Load command for counter 1, this register is ignored.

When reading from this register, the MSB value of the most recent Latch command for counter 0 will be returned. The value returned is NOT the value written to this register.

Page 0, Base + 15 Write Counter/Timer Control Register

Bit No.	7	6	5	4	3	2	1	0
Name	CTRNO	LATCH	GTDIS	GTEN	CTDIS	CTEN	LOAD	CLR
Reset	0	0	0	0	0	0	0	0

This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any ONE of bits 6 – 0 to select the desired operation for that counter. The other bits and associated functions are not affected. Thus only one operation can be performed at a time.

CTRNO Counter no., 0 or 1

LATCH Latch the selected counter so that its value may be read. The counter must be latched before it is read. Reading from registers 12-14 returns the most recently latched value. If you are reading Counter 1 data, read only Base + 12 and Base + 13. Any data in Base + 14 will be from the previous Counter 0 access.

GTDIS Disable external gating for the selected counter.

GTEN Enable external gating for the selected counter. If enabled, the associated gate signal GATE0 or GATE1 controls counting on the counter. If the GATEn signal is high, counting is enabled. If the GATEn signal is low, counting is disabled.

CTDIS Disable counting on the selected counter. The counter will ignore input pulses.

CTEN Enable counting on the selected counter. The counter will decrement on each input pulse.

LOAD Load the selected counter with the data written to Base + 12 through Base + 14 or Base + 12 and Base + 13 (depending on which counter is being loaded).

CLR Clear the current counter (set its value to 0).

Page 0, Base + 15 Read FPGA Revision Code

Bit No.	7	6	5	4	3	2	1	0
Name	REV7	REV6	REV5	REV4	REV3	REV2	REV1	REV0
Reset	0	0	0	0	0	0	0	0

REV7-0 Revision code, read as a 2-digit hex value. The first rev of this FPGA should be 0x48.

13.1.6 Page 1: AutoCalibration Control Regsiters

Page 1, Base + 12 Read/Write EEPROM / TrimDAC Data Register

Bit No.	7	6	5	4	3	2	1	0
Name	D7	D6	D5	D4	D3	D2	D1	D0
Reset	0	0	0	0	0	0	0	0

D7-0 Calibration data to be read or written to the EEPROM and/or TrimDAC.

During EEPROM or TrimDAC write operations, the data written to this register will be written to the selected device.

During EEPROM read operations this register contains the data to be read from the EEPROM and is valid after EEBUSY = 0.

The TrimDAC data cannot be read back.

Page 1, Base + 13 Read/Write EEPROM / TrimDAC Address Register

Bit No.	7	6	5	4	3	2	1	0
Name	X	A6	A5	A4	A3	A2	A1	A0
Reset	0	0	0	0	0	0	0	0

A6-A0 EEPROM / TrimDAC address.

The EEPROM recognizes address 0 – 127 using address bits A6 – A0. The TrimDAC only recognizes addresses 0 – 7 using bits A2 – A0. In each case remaining address bits will be ignored.

Page 1, Base + 14 Write Calibration Control Register

Bit No.	7	6	5	4	3	2	1	0
Name	EE_EN	EE_RW	RUNCAL	CALMUX	TDACEN	X	X	X
Reset	0	0	0	0	0	0	0	0

This register is used to initiate various commands related to autocalibration.

EE_EN EEPROM Enable. Writing a 1 to this bit will initiate a transfer to/from the EEPROM as indicated by the EE_RW bit.

EE_RW Selects read or write operation for the EEPROM: 0 = Write, 1 = Read.

RUNCAL Writing 1 to this bit causes the board to reload the calibration settings from EEPROM. See the description under the EEPROM / TrimDAC section. The FPGA does NOT reload the serial port configuration settings into bits SC3-0 since this could overwrite user settings.

CALMUX Calibration multiplexor enable. The cal mux is used to read precision on-board reference voltages that are used in the autocalibration process. It also can be used to read back the value of analog output 0.

1 = enable cal mux and disable user analog input channels

0 = disable cal mux, enable user inputs

TDACEN TrimDAC Enable. Writing 1 to this bit will initiate a transfer to the TrimDAC (used in the autocalibration process).

Page 1, Base + 14 Read Calibration Status Register

Bit No.	7	6	5	4	3	2	1	0
Name	0	TDBUSY	EEBUSY	CALMUX	TDACEN	0	0	0
Reset	0	0	0	0	0	0	0	0

TDBUSY TrimDAC busy indicator

0 User may access TrimDAC

1 TrimDAC is being accessed; user must wait

EEBUSY EEPROM busy indicator

0 User may access EEPROM

1 EEPROM is being accessed; user must wait

Page 1, Base + 15 Write EEPROM Access Key Register

The user must write the value 0xA5 (binary 10100101) to this register each time after setting the PAGE bit in order to get access to the EEPROM. This helps prevent accidental corruption of the EEPROM contents.

Writing 0xA6 to this register unlocks (enables) all enhanced features and sets FIFO depth to 1024 samples.

Writing 0xA7 to this register locks (disables) all enhanced features. This is the default power-on state. Writing 0xA7 to this register automatically halts any enhanced feature currently running, and internally clears all enhanced registers to their default state. The FIFO depth is 512 in this state.

Page 1, Base + 15 Read Page 1 ID Read-back

This register may be read back to confirm accesses to page 1. This register returns 0xA1.

13.1.7 Page 2 Expanded FIFO and AD/DA Control

Page 2, Base + 12 Read/Write Expanded FIFO Control

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	EXFIFO
Reset	0	0	0	0	0	0	0	0

EXFIFO Expanded FIFO enable. Default and reset value is 0, it is also set to 0 when enhanced features are disabled.

When EXFIFO is enabled (EXFIFO=1) dynamic threshold and depth tracking are disabled. The FIFO can then be tracked with the registers at base+6.

Page 2, Base + 13 Read/Write AD/DA Mode Control

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	DACPOLEN	DACPOL	ADPOL	ADPOLEN	ADSD	ADSDEN
Reset	0	0	0	0	0	0	0	0

This register functions as an AD Control Jumper override for the DAQ subsection. On reset values default to zero.

ADPOL Unipolar output setting. Set this bit (ADPOL=1) for Unipolar operation, clear this bit for Bipolar operation.

Reading this bit while ADPOLEN is set returns the last value written to ADPOL.Reading while ADPOLEN is clear returns the logical state of the pin.

ADPOLEN Enable ADPOL. When this bit is set, the ADPOL setting is output to the DAQ circuit.

ADSD Single Ended / Differential output setting. Set this bit (ADSD=1) for Single Ended operation, clear this bit for Differential operation.

Reading this bit while ADSDEN is set returns the last value written to ADSD.Reading while ADSDEN is clear returns the logical state of the pin.

ADSDEN Enable ADSD. When this bit is set, the ADSD setting is output to the DAQ circuit.

DACPOLEN Enable DACPOL. When this bit is set, the DACPOL setting is output to the DAC circuit.

0 = DAC Polarity is controlled by jumpers ( Default power on setting – DACLSEL pin in tri-state mode )

1 = DAC Polarity is controlled by software using DACPOL bit setting.

DACPOL DAC Polairty software override.

0 = DAC is set in UNIPOLAR mode

1 = DAC is set in BIPOLAR mode

Page 2, Base + 14 Read/Write AD Scan Interval

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	SCANINT
Reset	0	0	0	0	0	0	0	0

SCANINT Determines the interval between A/D conversions in scan mode:

0 10us (default)

1 5us

On power-up or reset, SCANINT returns to its default value of 0.

Page 2, Base + 15 Write DAQ LED Control

Bit No.	7	6	5	4	3	2	1	0
Name	DAQ_LED	-	-	SERCFG	SC3	SC2	SC1	SC0
Reset	0	0	0	0	EEPROM	EEPROM	EEPROM	EEPROM

DAQ_LED This signal controls the Blue LED ( FPGA_LED ) on the board. It should be set to 0 once the DAQ is configured and ready for use by the user.

0 = LED ON ( Default )

1 = LED OFF

SERCFG Serial port configuration control; on power-up / reset these bits are loaded from the EEPROM

1 = ignore DAQ_LED bit and write SC3-0 bits to serial configuration register

0 = write DAQ_LED bit and ignore SC3-0 bits

SC3-0 Serial port protocol configuration bits; these control the values on I/O pins P_SC3-0

Ports 1-2	SC1	SC0
Internal loop back	0	0
RS485	0	1
RS232	1	0
RS422	1	1

Ports 3-4	SC3	SC2
Internal loop back	0	0
RS485	0	1
RS232	1	0
RS422	1	1

Page 2, Base + 15 Read Page 2 ID Read-back

This register may be read back to confirm accesses to page 2. The register returns 0xA2.

13.1.8 Page 3: Board IDs

Page3, Base + 12 Write This is a Read only register

Any writes to this register are discarded.

Page3, Base + 12 Read RESERVED

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	-
Reset	0	0	0	0	0	0	0	0

This register provides a readback of 0x00 after RESET.

Page3, Base + 13 Write This is a Read only register.

Any writes to this register are discarded.

Page3, Base + 13 Read RESERVED

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	-
Reset	0	0	0	0	0	0	0	0

This register provides a readback of 0x00 after RESET.

Page3, Base + 14 Write This is a Read only register.

Any writes to this register are discarded.

Page3, Base + 14 Read Board Minor ID

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	-
Reset	0	0	0	0	0	0	0	0

This register may be read back to confirm accesses to page 3, FPGA Minor ID is 0x01.

Page3, Base + 15 Write This is a Read only register

Any writes to this register are discarded.

Page3, Base + 15 Read Board Major ID

Bit No.	7	6	5	4	3	2	1	0
Name	-	-	-	-	-	-	-	-
Reset	0	0	0	0	0	0	0	0

This register may be read back to confirm accesses to page 3, FPGA Major ID is 0x16.