DAQ Register Map

This page describes the register map provided on the DAQ subsystem available on Athena IV.

13.1 Data Acquisition Circuitry I/O Map

13.1.1 Overview

The data acquisition circuitry on Athena IV occupies 16 bytes in I/O memory space. The default address range is 280h (base address) to 28Fh.

13.1.2 Register Map Page Summary

The following table summarizes the DAC register functions. The registers are paged to allow access to enhanced functions. There are three register pages and the desired page is selected using the A/D gain and scan settings register, Base+3, bits PG0-PG1, provided the board is in enhanced mode.

Base +	Write Function	Read Function
DAQ Main Registers
0	Command	A/D LSB (bits 7-0)
1	Enhanced Mode Control/Page setting	A/D MSB (bits 15-8)
2	A/D Scan Channel	A/D Scan Channel L/H Read-back
3	A/D Gain and Scan Settings / Page Control	A/D-D/A Gain and Status Read-back
4	Interrupt / Counter Control	Interrupt / Counter Control Read-back
5	FIFO Threshold	FIFO Threshold Read-back
6	D/A LSB	FIFO Current Depth / FIFO Status
7	D/A MSB / DAC Channel	Interrupt and A/D Channel Read-back
8	Digital I/O Port A Output	Digital I/O Port A Input
9	Digital I/O Port B Output	Digital I/O Port B Input
10	DigitalI/OPort C Output	Digital I/O Port C Input
11	Digital I/O / DA Control	Digital I/O / DA Control Read-back
DAQ Registers Page 0: Counter/Timer Access
12	Counter/Timer D7-0	Counter/Timer D7-0
13	Counter/Timer D15-8	Counter/Timer D15-8
14	Counter/Timer D23-16	Counter/Timer D23-16
15	Counter/Timer Control	FPGA Revision Code
DAQ Registers Page 1: AutoCal Control
12	EEPROM/TrimDAC data latch	EEPROM/TrimDAC data read-back
13	EEPROM/TrimDAC address latch	EEPROM/TrimDAC address read-back
14	EEPROM/TrimDAC control register	EEPROM/TrimDAC status register
15	Special features unlock register0	Page 1 ID Read-back
DAQ Registers Page 2: Expanded FIFO and AD /DA Control
12	Expanded FIFO depth register	Expanded FIFO depth read-back
13	AD Mode Control	AD Mode Control Read-back
14	A/D scan interval	A/D scan interval
15	DAQ LED, Serial Port Control Register	Page 2 ID Read back
DAQ Registers Page 3: FPGA / Board ID
12	RESERVED	RESERVED
13	RESERVED	RESERVED
14	None, Read only	FPGA Minor ID Read-back
15	None, Read only	FPGA Major ID Read-back
CPLD Watchdog Registers
0	WDT trigger register	None, write only
1	WDT, counter register	None, write only
2	Watchdog Control register	Readback, see details
3	Chip select enable/disable	Readbacks the same written bits

N0TE: 1. Page 0, registers 0-11 are accessible when Page 1 or Page 2 are selected.

2. In the following tables, blank bits are not used. Writes to a blank bit have no effect and reads from a blank bit return a value of zero.

13.1.3 Register Map Bit Summary

Write Register Summary

Base +	7	6	5	4	3	2	1	0
Main Registers
0	STARTAD	RSTBRD	RSTDA	RSTFIFO	CLRDMA	CLRT	CLRD	CLRA
1							PG1	PG0
2	H3	H2	H1	H0	L3	L2	L1	L0
3	-	-	PG1	PG0	-	SCANEN	ADG1	ADG0
4	CKSEL1	FRQSEL1	FRQSEL0	ADCLK	DMAEN	TINTE	DINTE	AINTE
5	- / FT10	- / FT09	FT5/ FT08	FT4/ FT07	FT3/ FT06	FT2/ FT05	FT1/ FT04	FT0/ FT03
6	DA7	DA6	DA5	DA4	DA3	DA2	DA1	DA0
7	DACH1	DACH0	-	-	DA11	DA10	DA9	DA8
8	A7	A6	A5	A4	A3	A2	A1	A0
9	B7	B6	B5	B4	B3	B2	B1	B0
10	C7	C6	C5	C4	C3	C2	C1	C0
11	DIOCTR		DASIM	DIRA	DIRCH	-	DIRB	DIRCL
Page 0: Counter/Timer Access
Base +	7	6	5	4	3	2	1	0
12	CtrD7	CtrD6	CtrD5	CtrD4	CtrD3	CtrD2	CtrD1	CtrD0
13	CtrD15	CtrD14	CtrD13	CtrD12	CtrD11	CtrD10	CtrD9	CtrD8
14	CtrD23	CtrD22	CtrD21	CtrD20	CtrD19	CtrD18	CtrD17	CtrD16
15	CTRNO	LATCH	GTDIS	GTEN	CTDIS	CTEN	LOAD	CLR
Page 1: AutoCal Control
Base +	7	6	5	4	3