TABLE OF CONTENTS
This page shows the Table of Contents in the Athens IV SBC manual.
4.1 Processor Module
4.2 Power Supply Specifications
4.4 Ethernet
4.5 Video
4.6 Audio
4.7 USB2.0 Ports
4.8 USB3.0 Port
4.9 SATA
4.10 M.2 SATA Socket
4.11 Data Acquisition
4.12 Serial Ports
4.13 PCIe Link Routing
4.14 PC/104
4.17 LED Indicators
4.18 Jumpers
9.1 Power [J11]
9.4 Ethernet Ports
9.4.1 ETH-1 [J4]
9.4.2 ETH-2 [J19]
9.5 VGA [J25]
9.6 LVDS [J24]
9.8 Audio [J15]
9.10 USB3.0 [J7]
9.11 SATA [J26]
9.12 Data Acquisition (DAQ) [J14]
9.13 Serial Ports & Legacy I/O [J3]
9.14 JTAG [J16]
12.1 Serial Port & DIO pull-up/pull-down Configuration [JP1]
12.1.1 Select the protocol for the serial ports
12.1.2 Enable the pull-up or pull-down on the DIOs
12.2 LVDS Scan & Mapping [JP4]
12.3 LVDS LCD Panel Voltage Select [JP5]
12.5 ISA IRQ [JP6]
12.6 Termination Enable for Serial Ports [JP7, JP8]
12.7 SPI Select [JP9]
12.8 Watchdog Timer [J6]
12.10 Headless Mode [J25]
13.1 Data Acquisition Circuitry I/O Map
13.1.1 Overview
13.1.2 Register Map Page Summary
13.1.3 Register Map Bit Summary
13.1.4 Main Registers
13.1.5 Page 0: Counter / Timer Control Registers
13.1.6 Page 1: Autocalibration Control Registers
13.1.7 Page 2 Expanded FIFO and AD/DA Control
13.1.8 Page 3: Board IDs
13.2 Analog-to-Digital Input Ranges and Resolution
13.2.1 Overview
13.2.2 Input Range Selection
13.2.3 Input Range Table
13.2.3.1 Overview
13.2.3.2 Input Range Selection
13.2.3.3 Input Range Table
13.3 Performing an A/D Conversion
13.3.1 Introduction
13.3.2 Select the Input Channel
13.3.3 Select the Input Range
13.3.4 Wait for Analog Input Circuit to Settle
13.3.5 Perform an A/D Conversion on the Current Channel
13.3.6 Wait for the Conversion to Finish
13.3.7 Read the Data from the Board
13.3.8 Convert the numerical data to a meaningful value
13.4 A/D Scan, Interrupt and FIFO Operation
13.5 Digital-to-Analog Output Ranges and Resolution
13.5.1 Description
13.5.2 Resolution
13.5.3 Output Range Selection
13.5.4 D/A Conversion Formulas and Tables
13.5.5 Generating an Analog Output
13.5.6 Compute the D/A Code for the Desired Output Voltage
13.5.7 Write the Value to the Selected Output Channel Registers
13.5.8 Wait for the D/A to Update
13.5.9 Analog Circuit Calibration
13.7.1 Counter 0 – A/D Sample Control
13.7.2 Counter 1 – Counting/Totalizing Functions
13.7.3 Command Sequences
13.7.3.1 Load and Enable (Run) a Counter Sequence
13.7.3.2 Read a Counter Sequence
13.7.3.3 Disabling the Counter Gate Command
13.7.3.4 Clearing a Counter Sequence
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